1. Field of the Invention
The present invention relates to a packaged semiconductor device that is surface-mounted on a mother board.
2. Description of the Prior Art
A conventional packaged semiconductor device includes an integrated circuit formed on a semiconductor substrate such as a silicon wafer so as to realize device functions, lead connection pads (hereinafter referred to as pads) formed at predetermined intervals (so as to permit the bonding thereto of wires connecting to leads), protection circuits for preventing electrostatic destruction of the integrated circuit, wiring that electrically connects the pads to the integrated circuit by way of the projection circuits, and a protective film that covers all these components except the pads. All these are sealed in resin (see, for example, Japanese Patent Application Laid-Open No. 2001-217371).
The most effective way to reduce the cost of a packaged semiconductor device structured as described above is to reduce the size of the semiconductor substrate so as to increase the number of chips cut out of a single wafer and thereby reduce the unit cost. To achieve this, conventionally, techniques for making finer the process of forming integrated circuits have been eagerly developed for the purpose of increasing the integration density of integrated circuits.
It is true that, in a packaged semiconductor device structured as described above, increasing the integration density of the integrated circuit helps reduce the size of the semiconductor substrate and reduce the cost to a certain degree.
However, inconveniently, in a packaged semiconductor device structured as described above, when the integration density of the integrated circuit reaches a certain level, the size of the semiconductor substrate can no longer be reduced and therefore the cost can no longer be reduced because of the dimensions that need to be secured in the I/O region (the intervals at which the pads are formed and the depth of the protection circuits (the dimension thereof in the direction from the edge toward the middle of the substrate)). Considering the wire bonding accuracy today, the pads need to be formed at intervals of at least 110 to 140 μm. Moreover, considering the fact that the protection circuits cannot be formed right below the pads, where a high stress is applied during wire bonding, the I/O region needs to be at least several hundred μm deep.
As described above, in a packaged semiconductor device structured as described above, increasing the integration density of the integrated circuit from the current level with the development in the techniques of forming semiconductor chips results only in increasing the space for wiring, and does not lead to cost reduction. On the contrary, quite in a dilemma, the higher integration density requires more expensive fabrication equipment and thus increases the fabrication cost, and in addition lowers the yield rate. In some conventionally available products, the free space created as a result of the increased integration density is used to mount a memory array or the like to achieve higher cost performance. This structure, however, does not contribute to fundamental cost reduction, and therefore does not meet the user needs for further cost reduction.
Incidentally, in a packaged semiconductor device (see, for example, Japanese Patent Application Laid-Open No. 2000-223652) composed of a mother chip and a daughter chip connected together by way of bumps so as to form a chip-on-chip structure, the size of the daughter chip, which does not require pads for wire bonding, can be reduced as the integration density is increased. However, the purpose of adopting the chip-on-chip structure is to integrate together a plurality of chips fabricated by different processes, or to minimize the increase in the chip area resulting from larger-scale integrated circuits (through conversion to a vertical structure), or to enhance the productivity of different models by interchange of daughter chips. Thus, in a packaged semiconductor device having this structure, a large-scale integrated circuit is formed, quite naturally, also on the mother chip, and therefore, with the chip-on-chip structure, it is possible to reduce the cost of the daughter chip, but not the cost of the mother chip.
Also conventionally available are packaged semiconductor devices that adopt the techniques called CSP (chip scale package) and BGA (ball grid array) (see, for example, Japanese Patent Application Laid-Open No. 2000-012733) to reduce size and thereby reduce cost. However, to mount a packaged semiconductor device having such a structure directly on a mother board, it is necessary to use equipment that can accurately control its mounting position by camera recognition or the like, and introducing such equipment requires a large capital investment. This makes it difficult for a user with a small capital to introduce packaged semiconductor devices structured as described above.